Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

Seeding Rate and Row-Spacing Effects on Seed Yield and Yield Components of \u3cem\u3eLeymus chinensis\u3c/em\u3e (Trin.) Tzvel.

Chinese sheepgrass (Leymus chinensis (Trin.) Tzvel.) is widely distributed in the eastern portion of the Inner Mongolian Plateau and the Songnen Grassland of China. This grass is highly salt, cold and drought tolerant and has been the major source of forage for cows and other ruminants in China (Gao et al. 2012). Seed yield of this grass is very low under native conditions because of the low heading percentage and percentage of seed set (Wang et al. 2010). The Hexi Corridor, located in China’s northwestern Gansu Province, is the seed production center of China because of its dry, sunny climate and favorable irrigation conditions. Our field study was conducted to determine the optimum seeding rate and row-spacing for seed production of Chinese sheepgrass in the Hexi Corridor, where this grass has not been previously grown

Scientifically Grasping the New Media to Promote the Popularization of Marxism

Actively promoting the popularization of Marxism has always been an important part of the ideological and theoretical construction of the Communist Party of China (CPC). This approach has been vital for the CPC to lead its people to constantly create new situations in the development of socialism with Chinese characteristics. Currently, in the new era of comprehensively deepening reforms, the rapid development of new media has been one of the most important media tools in today’s society and also one of the significant carriers of the popularization of Marxism. The emergence and development of new media technologies provide a new platform and channel for the popularization of Marxism. Under the new media context, attaching importance to new media approaches, strengthening the talent construction, expanding the propaganda fronts, establishing the mass discourse system and improving the management system are critical to further promote the popularization of Marxism

Monitoring of Tsunami/Earthquake Damages by Polarimetric Microwave Remote Sensing Technique

Polarization characterizes the vector state of EM wave. When interacting with polarized wave, rough natural surface often induces dominant surface scattering; building also presents dominant double-bounce scattering. Tsunami/earthquake causes serious destruction just by inundating the land surface and destroying the building. By analyzing the change of surface and double-bounce scattering before and after disaster, we can achieve a monitoring of damages. This constitutes one basic principle of polarimetric microwave remote sensing of tsunami/earthquake. The extraction of surface and double-bounce scattering from coherency matrix is achieved by model-based decomposition. The general four-component scattering power decomposition with unitary transformation (G4U) has been widely used in the remote sensing of tsunami/earthquake to identify surface and double-bounce scattering because it can adaptively enhance surface or double-bounce scattering. Nonetheless, the strict derivation in this chapter conveys that G4U cannot always strengthen the double-bounce scattering in urban area nor strengthen the surface scattering in water or land area unless we adaptively combine G4U and its duality for an extended G4U (EG4U). Experiment on the ALOS-PALSAR datasets of 2011 great Tohoku tsunami/earthquake demonstrates not only the outperformance of EG4U but also the effectiveness of polarimetric remote sensing in the qualitative monitoring and quantitative evaluation of tsunami/earthquake damages

Electronic properties and quantum transports in functionalized graphene Sierpinski carpet fractals

Recent progress in controllable functionalization of graphene surfaces enables the experimental realization of complex functionalized graphene nanostructures, such as Sierpinski carpet (SC) fractals. Herein, we model the SC fractals formed by hydrogen and fluorine functionalized patterns on graphene surfaces, namely, H-SC and F-SC, respectively. We then reveal their electronic properties and quantum transport features. From calculated results of the total and local density of state, we find that states in H-SC and F-SC have two characteristics: (i) low-energy states inside about |E/t|<1 (with t as the near-neighbor hopping) are localized inside free graphene regions due to the insulating properties of functionalized graphene regions, and (ii) high-energy states in F-SC have two special energy ranges including -2.3<E/t<-1.9 with localized holes only inside free graphene areas and 3<E/t<3.7 with localized electrons only inside fluorinated graphene areas. The two characteristics are further verified by the real-space distributions of normalized probability density. We analyze the fractal dimension of their quantum conductance spectra and find that conductance fluctuations in these structures follow the Hausdorff dimension. We calculate their optical conductivity and find that several additional conductivity peaks appear in high energy ranges due to the adsorbed H or F atoms